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    National Tsing Hua University Institutional Repository > 電機資訊學院 > 資訊工程學系 > 會議論文  >  TSV redundancy: Architecture and design issues in 3D IC


    Please use this identifier to cite or link to this item: http://nthur.lib.nthu.edu.tw/dspace/handle/987654321/65823


    Title: TSV redundancy: Architecture and design issues in 3D IC
    Authors: Ang-Chih Hsieh;TingTing Hwang;Ming-Tung Chang;Min-Hsiu Tsai;Chih-Mou Tseng;Li, H.-C.
    教師: 黃婷婷
    Date: 2010
    Relation: Design,Automation & Test in Europe Conference & Exhibition (DATE),2010,Issue Date: 8-12 March 2010,On page(s): 166 - 171
    Keywords: TSV redundancy
    Architecture
    design issues
    Abstract: 3D technology provides many benefits including high density, high band-with, low-power, and small form-factor. Through Silicon Via (TSV), which provides communication links for dies in vertical direction, is a critical design issue in 3D integration. Just like other components, the fabrication and bonding of TSVs can fail. A failed TSV may cause a number of known-good-dies that are stacked together to be discarded. This can severely increase the cost and decrease the yield as the number of dies to be stacked increases. A redundant TSV architecture with reasonable cost for ASICs is proposed in this paper. Design issues including recovery rate and timing problem are addressed. Based on probabilistic models, some interesting findings are reported. First, the probability that three or more TSVs are failed in a tier is less than 0.002%. Assumption of that there are at most two failed TSVs in a tier is sufficient to cover 99.998% of all possible faulty free and faulty cases. Next, with one redundant TSV allocated to one TSV block, limiting the number of TSVs in each TSV block to be no greater than 50 and 25 leads to 90% and 95% recovery rates when 2 failed TSVs are assumed. Finally, analysis on overall yield shows that the proposed design can successfully recover most of the failed chips and increase the yield of TSV bonding to 99.99%. This can effectively reduce the cost of manufacturing 3D ICs.
    URI: http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=5457218&tag=1
    http://nthur.lib.nthu.edu.tw/dspace/handle/987654321/65823
    Appears in Collections:[資訊工程學系] 會議論文

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