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    National Tsing Hua University Institutional Repository > 電機資訊學院 > 資訊工程學系 > 期刊論文 >  Overlapped decompositions for communication complexity driven multilevel logic synthesis


    Please use this identifier to cite or link to this item: http://nthur.lib.nthu.edu.tw/dspace/handle/987654321/65842


    Title: Overlapped decompositions for communication complexity driven multilevel logic synthesis
    Authors: Kuo-Hua Wang;Ting-Ting Hwang;Cheng Chen
    教師: 黃婷婷
    Date: 1993
    Publisher: Oxford University Press
    Relation: IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS,Volume E76D,Issue 9,Pages 1075-1084,SEP 1993
    Keywords: communication complexity
    delays
    logic design
    multilevel logic synthesis
    circuit size
    overlapped decomposition
    area
    delay
    Abstract: Reducing communication complexity is a viable approach to multilevel logic synthesis. A communication complexity based approach was proposed previously. In the previous works, only disjoint input decomposition was considered. However, for certain types of circuits, the circuit size can be reduced by using overlapped decomposition. The authors consider overlapped decompositions. Some design issues for overlapped decompositions such as detecting `globals' and deriving subfunctions are addressed. Moreover, the decomposition don't cares (DDC) is considered for improving the decomposed results. By using these techniques together, the area and delay of circuits can be further minimized
    URI: http://www.oxfordjournals.org/
    http://nthur.lib.nthu.edu.tw/dspace/handle/987654321/65842
    Appears in Collections:[資訊工程學系] 期刊論文

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