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    National Tsing Hua University Institutional Repository > 電機資訊學院 > 資訊工程學系 > 期刊論文 >  Post-routing redundant via insertion for yield/reliability improvement

    Please use this identifier to cite or link to this item: http://nthur.lib.nthu.edu.tw/dspace/handle/987654321/67028

    Title: Post-routing redundant via insertion for yield/reliability improvement
    Authors: K.-Y. Lee;T.-C. Wang
    教師: 王廷基
    Date: 2006
    Publisher: Institute of Electrical and Electronics Engineers
    Relation: Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC),Yokohama,Japan,January 2006,pp. 303-308
    Keywords: Post-routing redundant
    Abstract: Reducing the yield loss due to via failure is one of the important problems in design for manufacturability. A well known and highly recommended method to improve via yield/reliability is to add redundant vias. In this paper we study the problem of post-routing redundant via insertion and formulate it as a maximum independent set (MIS) problem. We present an efficient graph construction algorithm to model the problem, and an effective MIS heuristic to solve the problem. The experimental results show that our MIS heuristic inserts more redundant vias and distributes them more uniformly among via layers than a commercial tool and an existing method. The number of inserted redundant vias can be increased by up to 21.24%. Besides, since redundant vias can be classified into on-track and off-track ones, and on-track ones have better electrical properties, we also present two methods (one is modified from the MIS heuristic, and the other is applied as a post processor) to increase the amount of on-track redundant vias. The experimental results indicate that both methods perform very well.
    URI: http://nthur.lib.nthu.edu.tw/dspace/handle/987654321/67028
    Appears in Collections:[資訊工程學系] 期刊論文

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