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    National Tsing Hua University Institutional Repository > 電機資訊學院 > 資訊工程學系 > 會議論文  >  Fault equivalence analysis and reduction of two level test set for multilevel logic synthesis


    Please use this identifier to cite or link to this item: http://nthur.lib.nthu.edu.tw/dspace/handle/987654321/67047


    Title: Fault equivalence analysis and reduction of two level test set for multilevel logic synthesis
    Authors: Wen-Jun Hsu;Wen-Zen Shen;Jyuo-Min Shyu
    教師: 徐爵民
    Date: 1992
    Publisher: Institute of Electrical and Electronics Engineers
    Relation: 1992 IEEE International Symposium on Circuits and Systems (Cat. No.92CH3139-3),p 415-18 vol.1,3-6 May 1992
    Keywords: fault location
    logic design
    logic testing
    many-valued logics
    Abstract: The relationship between faults in a synthesized multilevel network and in its collapsed two-level network is analyzed. A program to select a proper set of faults in the collapsed two-level network from the synthesized multilevel network is implemented. The test for selected faults will detect all single stuck-at faults of the synthesized multilevel network. The number of generated tests is about 50% less than the number for the two-level complete test set
    URI: http://www.ieee.org/
    http://nthur.lib.nthu.edu.tw/dspace/handle/987654321/67047
    Appears in Collections:[資訊工程學系] 會議論文

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