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    National Tsing Hua University Institutional Repository > 電機資訊學院 > 資訊工程學系 > 會議論文  >  An efficient placement algorithm for run-time reconfigurable embedded system


    Please use this identifier to cite or link to this item: http://nthur.lib.nthu.edu.tw/dspace/handle/987654321/67493


    Title: An efficient placement algorithm for run-time reconfigurable embedded system
    Authors: Radha Guha;Nader Bagherzadeh;Pai Chou
    教師: 周百祥
    Date: 2007
    Publisher: 19th IASTED International Conference on Parallel and Distributed Computing and Systems
    Relation: Proceedings of the IASTED Parallel and Distributed Computing and Systems (PDCS) 2007 Conference,Cambridge,MAssachusetts,USA,November 19-21,2007
    Keywords: Applications
    Embedded systems
    Field programmable gate arrays
    Integrated circuits
    Abstract: In the era of application convergence, the small handheld battery-powered portable devices are required to multiplex their limited hardware resources between many complex applications. Our first contribution in this paper is a modular and block based configuration architecture for modern FPGAs like Xilinx's Virtex-4 and Virtex-5 devices, to increase multi-tasking capabilities, power savings and performance improvement of applications for mobile handsets. Our second contribution is an on-line placement algorithm based on bin packing, called Hierarchical Best Fit Ascending (HBFA) algorithm, which is more efficient than Best Fit (BF) algorithm for mapping a dynamic task list onto the FPGA. The overall time complexity of the proposed on-line placement algorithm, HBFA, is reduced to O(n) in comparison to the complexity of BF algorithm which is O(n2). The placement solution provided by HBFA algorithm is also better than that of BF algorithm
    URI: https://www.actapress.com/Abstract.aspx?paperId=31980
    http://www.iasted.org/conferences/pastinfo-590.html
    http://nthur.lib.nthu.edu.tw/dspace/handle/987654321/67493
    Appears in Collections:[資訊工程學系] 會議論文

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