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    National Tsing Hua University Institutional Repository > 電機資訊學院 > 電機工程學系 > 會議論文  >  A new buffer-memory architecture for FFT computation


    Please use this identifier to cite or link to this item: http://nthur.lib.nthu.edu.tw/dspace/handle/987654321/67948


    Title: A new buffer-memory architecture for FFT computation
    Authors: Sheng-Ju Ku;Chin-Liang Wang
    教師: 王晉良
    Date: 2005
    Publisher: International Symposium on Communications
    Relation: Proceedings of the 2005 International Symposium on Communications, Kaohsiung, Taiwan, Nov. 20-22, 2005
    Keywords: DFT
    DVB
    FFT
    OFDM
    Memory-base design
    VDSL
    Abstract: Memory-based designs of the fast Fourier transform (FFT) processor are attractive for single-chip implementation. Basically, their architectures can be divided into three types: single-memory design, dual-memory design, and buffer-memory design. Among them, the buffer-memory design can balance the trade-off between memory size and control circuit complexity. In this paper, we present a new buffer-memory architecture for realizing the radix-2 decimation-in-time N-point FFT algorithm. As compared with previous related works, the proposed design reaches the same throughput performance of two transform samples per log2N+1 clock cycles and 100% utilization efficiency in butterfly unit with fewer ROM access times of N-2. It is rather attractive for long-length FFT applications, such as very-high-rate digital subscriber lines and digital video broadcasting.
    Relation Link: http://www.ee.bilkent.edu.tr/~signal/defevent/papers/cr1282.pdf
    URI: http://nthur.lib.nthu.edu.tw/dspace/handle/987654321/67948
    Appears in Collections:[電機工程學系] 會議論文

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