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    National Tsing Hua University Institutional Repository > 電機資訊學院 > 電機工程學系 > 會議論文  >  RAMSES-D: DRAM fault simulator supporting weighted coupling fault

    Please use this identifier to cite or link to this item: http://nthur.lib.nthu.edu.tw/dspace/handle/987654321/68213

    Title: RAMSES-D: DRAM fault simulator supporting weighted coupling fault
    Authors: Hsing, Yu-Tsao;Wu, Song-Guang;Wu, Cheng-Wen
    教師: 吳誠文
    Date: 2007
    Publisher: Institute of Electrical and Electronics Engineers
    Relation: 17th IEEE International Workshop on Memory Technology, Design, and Testing, MTDT 2007, Pages 33-38
    Keywords: RAMSES-D
    Abstract: Memory fault simulator is an important tool for memory test sequence optimization. Traditionally, we use fault count to calculate fault coverage. However, it cannot represent accurately the real coupling fault distribution. In this paper, we adopt the concept of weighted coupling fault targeting DRAM.We propose a weighted fault coverage function with assigning weight parameters to coupling faults. With the weighted function, we can use physical information to calculate coupling fault coverage. Experimental result shows that the weight of intra-word coupling fault can be 10% to 14%; while the original fault count method cannot distinguish the degree of importance between different memory configurations. ©2007 IEEE.
    Relation Link: http://www.ieee.org/
    URI: http://nthur.lib.nthu.edu.tw/dspace/handle/987654321/68213
    Appears in Collections:[電機工程學系] 會議論文

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