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    National Tsing Hua University Institutional Repository > 電機資訊學院 > 電機工程學系 > 會議論文  >  Memory repair by die stacking with through silicon vias


    Please use this identifier to cite or link to this item: http://nthur.lib.nthu.edu.tw/dspace/handle/987654321/68218


    Title: Memory repair by die stacking with through silicon vias
    Authors: Chou, Yung-Fa;Kwai, Ding-Ming;Wu, Cheng-Wen
    教師: 吳誠文
    Date: 2009
    Publisher: Institute of Electrical and Electronics Engineers
    Relation: 2009 IEEE International Workshop on Memory Technology, Design, and Testing, MTDT 2009, August 31, 2009 - September 2, 2009, Pages 53 - 58
    Keywords: Dies
    Interconnection networks
    Profitability
    Repair
    Three dimensional
    Abstract: As we adopt more advanced process technologies, the volume production of memory devices, such as DRAM and Flash, becomes more difficult. It seems inevitable that during the ramp-up period, the initial manufacturing yield will be lower, and it takes more time and effort to improve the yield to a reasonable level. Although redundancy can be used to improve the yield eventually, the reserved spares may not be enough at the beginning, so most dies may be irreparable. We propose the usage of three-dimensional (3D) integration to achieve yield enhancement. Through silicon vias (TSVs) patch good memory blocks in a bad die with those in another bad die by bonding them together and enabling the built-in circuit. The die stack has the same functionality, though slightly increases delay and power. Nevertheless, if the production yield takes a long time to achieve, the 3D patched memory is deemed to be a transitional-period product. It does help to shorten time-to-market and make the irreparable memories profitable. © 2009 IEEE.
    Relation Link: http://www.ieee.org/
    URI: http://nthur.lib.nthu.edu.tw/dspace/handle/987654321/68218
    Appears in Collections:[電機工程學系] 會議論文

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