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    National Tsing Hua University Institutional Repository > 電機資訊學院 > 電機工程學系 > 會議論文  >  A low noise amplifier co-designed with ESD protection circuit in 65-nm CMOS


    Please use this identifier to cite or link to this item: http://nthur.lib.nthu.edu.tw/dspace/handle/987654321/68778


    Title: A low noise amplifier co-designed with ESD protection circuit in 65-nm CMOS
    Authors: M. Tasi;S. Hsu;K. Tan
    教師: 徐碩鴻
    Date: 2009
    Publisher: Institute of Electrical and Electronics Engineers
    Relation: IEEE MTT-S Int. Microwave Symp., Boston, 7-12 June 2009, Pages 573-576
    Keywords: amplifier
    ESD
    circuit
    CMOS
    Abstract: By means of co-design ESD protection circuit as the low noise amplifier (LNA) input matching network, a 5.8-GHz LNA with excellent ESD and noise performances is demonstrated by a 65-nm CMOS technology. The diode-based ESD design with a power clamp can achieve 4 kV human body model (HBM) performance while the noise figure (NF) is only 0.05 dB higher than that of the LNA without the extra ESD blocks. Under a supply voltage of 1.2 V and drain current of 7 mA, the ESD-LNA has a NF of 1.9 dB with an associated power gain of 18 dB. The input third-order intercept point (IIP3) is -11 dBm and the input and output insertion losses are below -16 dB and -20 dB, respectively.
    Relation Link: http://www.ieee.org/
    URI: http://nthur.lib.nthu.edu.tw/dspace/handle/987654321/68778
    Appears in Collections:[電機工程學系] 會議論文

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