A 90 nm 256 Kb NAND-ROM using read-1 noise elimination and read-0 sensing-margin-expanding schemes is functional at 0.29 V and 3 MHz with 100% code-coverage and 5% area overhead. This work reduces the delay-per-BL-length, energy-per-bit at VDDmin, and VDDmin-delay-product by 3000Ã, 4Ã and 3700Ã, respectively, compared to previous low-voltage ROMs.