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    National Tsing Hua University Institutional Repository > 電機資訊學院 > 電機工程學系 > 會議論文  >  Inductive Fault Analysis and Fault Modeling of NOR Array Flash Memories


    Please use this identifier to cite or link to this item: http://nthur.lib.nthu.edu.tw/dspace/handle/987654321/68875


    Title: Inductive Fault Analysis and Fault Modeling of NOR Array Flash Memories
    Authors: J.-N. Ko;J.-R. Huang;T.Y. Chang
    教師: 張慶元
    Date: 1999
    Publisher: Nanyang Technological University
    Relation: 8th International Symposium on Integrated Circuits, NTU, Sept. 8-10 1999, Volume 8, Pages 60-63
    Keywords: Floating gate
    Inductive fault analysis
    NOR-type flash memory
    Abstract: The famous NOR-type flash memory structure is included to develop flash memory fault model in this work. The 13 realistic faults consisted of 11 functional faults and 2 parametric faults have been proven to likely occur if some undesired dust particles are dropped on the physical masks in natural manufacturing process. The proposed fault models will facilitate test engineers to put their test effort on effective and accurate fault models instead of utilizing classical "reduced functional fault models" to test flash memories. The classical fault model, which does not concern the physical operation and detail layout, may cost a lot of test time but fail to gain higher fault coverage. But such tragedies would not happen if the proposed fault model is adopted because the proposed one is based on the physical geometry of NOR-type flash memory, and verified by device simulator TMA/Medici.
    Relation Link: www.ntu.edu.sg
    URI: http://nthur.lib.nthu.edu.tw/dspace/handle/987654321/68875
    Appears in Collections:[電機工程學系] 會議論文

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