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    National Tsing Hua University Institutional Repository > 電機資訊學院 > 電機工程學系 > 會議論文  >  A Novel MUX-FF Circuit for Low Power and High Speed Serial Link Interfaces

    Please use this identifier to cite or link to this item: http://nthur.lib.nthu.edu.tw/dspace/handle/987654321/69046

    Title: A Novel MUX-FF Circuit for Low Power and High Speed Serial Link Interfaces
    Authors: Wei-Yu Tsai;Ching-Te Chiu;Jen-Ming Wu;Shuo-Hung Hsu;Yar-Sun Hsu
    教師: 許雅三
    Date: 2010
    Publisher: Institute of Electrical and Electronics Engineers
    Relation: Circuits and Systems (ISCAS), Proceedings of 2010 IEEE International Symposium on, Paris, France, May 30-June 2 2010, Pages 4305 - 4308
    Keywords: MUX-FF
    Abstract: In this paper, a novel multiplexer-flip-flop (MUX-FF) topology using the current mode logic (CML) is presented. A CML multiplexer-latch (MUX-latch) is proposed by combining a multiplexer and the loopback storage part of a latch into a single module so that the buffer part of a latch can be removed. A MUX-FF is implemented by cascading two stages of MUX-latches. The output of a MUX-FF is edge-triggered, so it is insensitive to input noise. All the paths from inputs to the output are symmetric. Power and area can be reduced due to the removal of DFFs. Simulation results show that a MUX-FF can achieve a similar frequency as a conventional tree-type MUX by saving 56% of area and 72% of power consumption.
    Relation Link: http://www.ieee.org/
    URI: http://nthur.lib.nthu.edu.tw/dspace/handle/987654321/69046
    Appears in Collections:[電機工程學系] 會議論文

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