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    National Tsing Hua University Institutional Repository > 電機資訊學院 > 電機工程學系 > 會議論文  >  A 10 Gb/s Wide-Band Current-Mode Logic I/O Interface for High-Speed Interconnect in 0.18μm CMOS Technology

    Please use this identifier to cite or link to this item: http://nthur.lib.nthu.edu.tw/dspace/handle/987654321/69059

    Title: A 10 Gb/s Wide-Band Current-Mode Logic I/O Interface for High-Speed Interconnect in 0.18μm CMOS Technology
    Authors: Ching-Te Chiu;Jen-Ming Wu;YarSun Hsu;Shuo-Hung Hsu;Min-Sheng Kao;Chih-Hsien Jen
    教師: 許雅三
    Date: 2005
    Publisher: Institute of Electrical and Electronics Engineers
    Relation: SOC Conference, 2005. Proceedings. IEEE International, Washington DC, USA, 25-28 Sept. 2005, Pages 257
    Keywords: Wide-Band
    Abstract: A low power, area-efficient 10 Gb/s wide-band current-mode logic (CML) I/O interface for high-speed interconnect is presented in this paper. This interface consists of input equalizer, limiting amplifier, CML buffer and output voltage-peaking circuit. Several wide-band techniques for this work are adopted to broaden the bandwidth and realize the circuit in 10Gb/s operation. The techniques include PMOS active load inductive-peaking, active feedback and Cherry-Hooper topology. These techniques can reduce 80% of the circuit area compared to the circuit area with on-chip inductors. The integration of the input equalizer and output voltage-peaking is also verified in this paper to provide robust I/O interface for high-speed interconnect and compensate transmission signal attenuation in the backplane. This work has been implemented in a 0.18μm CMOS technology. The total power consumption of the I/O interface is only 70mW. The area of input and output interface are 0.02mm2and 0.008mm2. The input interface can operate at 10Gb/s with 40dB input dynamic range and 4mV input sensitivity.
    Relation Link: http://www.lw30.com/2011071192449453.html
    URI: http://nthur.lib.nthu.edu.tw/dspace/handle/987654321/69059
    Appears in Collections:[電機工程學系] 會議論文

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