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    National Tsing Hua University Institutional Repository > 電機資訊學院 > 電機工程學系 > 會議論文  >  A sub-word parallel digital signal processor for wireless communication systems

    Please use this identifier to cite or link to this item: http://nthur.lib.nthu.edu.tw/dspace/handle/987654321/69504

    Title: A sub-word parallel digital signal processor for wireless communication systems
    Authors: Yuan-Hao Huang;Tzi-Dar Chiueh
    教師: 黃元豪
    Date: 2002
    Publisher: Institute of Electrical and Electronics Engineers
    Relation: 2002 IEEE Asia-Pacific Conference on ASIC. Proceedings (Cat. No.02EX547), Taipei, Taiwan, 6-8 Aug. 2002, Pages 287-90
    Keywords: digital signal processor
    subword parallel MAC
    FFT butterfly
    Abstract: In this paper, we propose a programmable fixed-point digital signal processor for wireless communications. The architecture of the processor is designed according to the computation requirements of modern communication systems. A decimation-in-frequency (DIF) butterfly unit is built in the processor to enhance the processing capability of FFT operations needed in orthogonal-frequency-division-multiplexing (OFDM) systems. In addition, the butterfly unit can be reconfigured to accelerate squared-difference and add-compare-select calculation in the Viterbi algorithms. A new subword parallel complex-valued multiply-and-accumulate (MAC) architecture is proposed to execute complex/real and single/double precision operations, making it suitable for different requirements of signal formats in signal processing for communication transceivers.
    Relation Link: http://www.ieee.org/
    URI: http://nthur.lib.nthu.edu.tw/dspace/handle/987654321/69504
    Appears in Collections:[電機工程學系] 會議論文

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