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    National Tsing Hua University Institutional Repository > 電機資訊學院 > 電機工程學系 > 會議論文  >  A 1.2-V CMOS Limiter / RSSI / Demodulator for Low-IF FSK Receiver

    Please use this identifier to cite or link to this item: http://nthur.lib.nthu.edu.tw/dspace/handle/987654321/69643

    Title: A 1.2-V CMOS Limiter / RSSI / Demodulator for Low-IF FSK Receiver
    Authors: Yi-Chung Chen;Yi-Chang Wu;Po-Chiun Huang
    教師: 黃柏鈞
    Date: 2007
    Publisher: Institute of Electrical and Electronics Engineers
    Relation: Custom Integrated Circuits Conference, 2007. CICC '07. IEEE, 16-19 Sept. 2007, Pages 217 - 220
    Keywords: CMOS integrated circuits
    circuit stability
    delay lock loops
    frequency shift keying
    Abstract: This paper presents low-voltage low-power limiter, RSSI, and demodulator designs for a low-IF wireless FSK receiver. The IF is located at 3 MHz. The FSK demodulator is implemented by a delay-locked loop associated with the techniques of digital offset cancellation and modified phase-frequency detection. The demodulated data can be recovered with one-clock latency. The circuits in limiter and RSSI are all pseudo differential to minimize the requirement of the voltage headroom. Each gain cell with feedforward offset cancellation and common mode stabilization circuits can make sure its functionality against device mismatch. The chip uses a standard 0.18 mum CMOS process. The active area is 0.11 mm2. With a single 1.2-V power supply, measurement results show that the 55 dB gain, 15 MHz bandwidth limiter and the RSSI consume 1.9 mA. The FSK demodulator part consumes 300 muA.
    Relation Link: http://www.ieee.org/
    URI: http://nthur.lib.nthu.edu.tw/dspace/handle/987654321/69643
    Appears in Collections:[電機工程學系] 會議論文

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