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    National Tsing Hua University Institutional Repository > 電機資訊學院 > 電機工程學系 > 會議論文  >  A 1-V Fully Differential Amplifier with Buffered Nested-Miller Compensation


    Please use this identifier to cite or link to this item: http://nthur.lib.nthu.edu.tw/dspace/handle/987654321/69663


    Title: A 1-V Fully Differential Amplifier with Buffered Nested-Miller Compensation
    Authors: M.-H. Shen;P.-M. Wang;L.-W. Wang;P.-C. Huang
    教師: 黃柏鈞
    Date: 2009
    Publisher: Institute of Electrical and Electronics Engineers (IEEE)
    Relation: SoC Design Conference (ISOCC), 2009 International, Busan, 22-24 Nov. 2009, Pages 309 - 312
    Keywords: Amplifier
    Nested-Miller
    Abstract: This paper presents a 1-V three-stage fully differential amplifier with buffered nested-Miller compensation. A transconductance stage is inserted in the feedback path to eliminate the right half plane (RHP) zero. In addition, a feedforward transconductance is used to enhance output large signal response. Using a standard 0.35-¿m CMOS technology, measurement results demonstrate that DC gain greater than 90dB, gain-bandwidth product of 4.57MHz, and phase margin of 55° is achieved with 100pF output loads. The settling time for a 1-Vpp step is 2¿s. All the circuits dissipate 110¿W under a single 1-V power supply.
    Relation Link: http://www.ieee.org/
    URI: http://nthur.lib.nthu.edu.tw/dspace/handle/987654321/69663
    Appears in Collections:[電機工程學系] 會議論文

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