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    Title: A low-power SRAM for Viterbi decoder in wireless communication
    Authors: Shin-Pao Cheng;Shi-Yu Huang
    Teacher: 黃錫瑜
    Date: 2008
    Publisher: Institute of Electrical and Electronics Engineers
    Relation: Consumer Electronics, IEEE Transactions, Institute of Electrical and Electronics Engineers, Volume 54, Issue 2, May 2008, Pages 290 - 295
    Keywords: SRAM
    Abstract: In a consumer electronic device, the embedded memories often consume a major portion of the total power. In this paper, we present a low-power SRAM design for a Viterbi decoder, featuring a quiet-bitline architecture with two techniques. Firstly, we use a one-side driving scheme for the write operation to prevent the excessive full-swing charging on the bitlines. Secondly, we use a precharge-free pulling scheme for the read operation so as to keep all bitlines at low voltages at all times. Silicon results shows that such architecture can lead to a significant 70%power reduction over a self-designed baseline low-power SRAM macro.
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    Appears in Collections:[Department of Electrical Engineering] EE Journal / Magazine Articles

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