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    National Tsing Hua University Institutional Repository > 電機資訊學院 > 電機工程學系 > 期刊論文 >  P-P-N Based 10T SRAM Cell for Low-Leakage and Resilient Sub-Threshold Operation


    Please use this identifier to cite or link to this item: http://nthur.lib.nthu.edu.tw/dspace/handle/987654321/71450


    Title: P-P-N Based 10T SRAM Cell for Low-Leakage and Resilient Sub-Threshold Operation
    Authors: C.-H. Lo;S.-Y. Huang
    教師: 黃錫瑜
    Date: 2011
    Publisher: Institute of Electrical and Electronics Engineers
    Relation: IEEE Journal of Solid-State Circuits, Institute of Electrical and Electronics Engineers, Volume 46, Issue 3, March, 2011, Pages 695-704
    Keywords: P-P-N
    SRAM
    Low-Leakage
    Sub-Threshold
    Abstract: SRAM has been under its renovation stage recently, aiming to withstand the ever-increasing process variation as well as to support ultra-low-power applications using even subthreshold supply voltages. We present in this paper a novel P-P-N-based 10T SRAM cell, in which the latch is formed essentially by a cross-coupled P-P-N inverter pair. This type of cell can operate at a voltage as low as 285 mV while still demonstrating high resilience to process variation. Its noise margin has been elevated in not only the hold state, but also the read operations. As compared to previous 10T SRAM cells, our cell excels in particular in two aspects: 1) ultra-low cell leakage, and 2) high immunity to the data-dependent bitline leakage. The second merit makes it especially suitable for an SRAM macro with long bitlines - a property often desirable in order to achieve high density. We have fabricated and validated its performance through a 16 Kb SRAM test chip using the UMC 90 nm process technology.
    Relation Link: http://www.ieee.org/
    URI: http://nthur.lib.nthu.edu.tw/dspace/handle/987654321/71450
    Appears in Collections:[電機工程學系] 期刊論文

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