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    National Tsing Hua University Institutional Repository > 電機資訊學院 > 電機工程學系 > 期刊論文 >  Test algorithm and bist design for mram write disturbance fault


    Please use this identifier to cite or link to this item: http://nthur.lib.nthu.edu.tw/dspace/handle/987654321/71701


    Title: Test algorithm and bist design for mram write disturbance fault
    Authors: Chen, Ching-Yi;Lo, Wan-Yu;Su, Chin-Lung;Wu, Cheng-Wen
    教師: 吳誠文
    Date: 2008
    Publisher: Chinese Institute of Electrical Engineering(中國電機工程學會)
    Relation: International Journal of Electrical Engineering, Chinese Institute of Electrical Engineering(中國電機工程學會), Volume 15, Issue 2, April 2008, Pages 63-70
    Keywords: Algorithms
    Boolean functions
    Integrated circuit testing
    Magnetic fields
    Magnetic storage
    Optical design
    Random access storage
    Static random access storage
    Testing
    Abstract: The write disturbance fault (WDF) model is a fault model specific to MRAM which implies that the data stored in the MRAM cells is changed due to excessive magnetic field during a Write operation. March tests have high coverage for conventional RAM faults. However, they do not detect all WDFs. To improve the quality and yield of MRAM, we propose a new test algorithm to detect WDF for MRAM in this paper, and further apply the proposed algorithm to test MRAM chips. Fault coverage of proposed test algorithm is higher than that of traditional March test algorithms. Also, we develop a built-in self-test (BIST) circuit that supports the proposed test method. A 128Kb MRAM prototype chip with proposed BIST circuit has been designed and fabricated using a special 0.15 um CMOS technology.
    Relation Link: http://larc.ee.nthu.edu.tw/~wylo/IJEE08.pdf
    http://www.ciee.org.tw/
    URI: http://nthur.lib.nthu.edu.tw/dspace/handle/987654321/71701
    Appears in Collections:[電機工程學系] 期刊論文

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