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    National Tsing Hua University Institutional Repository > 電機資訊學院 > 電機工程學系 > 期刊論文 >  A 10Gb/s CML I/O Circuit for Backplane Interconnect in 0.18μm CMOS Technology

    Please use this identifier to cite or link to this item: http://nthur.lib.nthu.edu.tw/dspace/handle/987654321/71872

    Title: A 10Gb/s CML I/O Circuit for Backplane Interconnect in 0.18μm CMOS Technology
    Authors: M.-S. Kao;J.-M. Wu;C.-H.Lin;F.-T. Chen;C.-T. Chiu;S.-H. Hsu
    教師: 吳仁銘
    Date: 2009
    Publisher: Institute of Electrical and Electronics Engineers
    Relation: IEEE Transactions on VLSI Systems, Institute of Electrical and Electronics Engineers, Volume 17, Issue 5, May 2009
    Keywords: Circuit
    Abstract: A 10-Gb/s current mode logic (CML) input/output (I/O) circuit for backplane interconnect is fabricated in 0.18-µm 1P6M CMOS process. Comparing with conventional I/O circuit, this work consists of input equalizer, limiting amplifier with active-load inductive peaking, duty cycle correction and CML output buffer. To enhance circuit bandwidth for 10-GB/s operation, several techniques include active load inductive peaking and active feedback with current buffer in Cherry-Hooper topology. With these techniques, it reduces 30%-65% of the chip area comparing with on-chip inductor peaking method. This design also passes the interoperability test with switch fabric successfully. It provides 600-mVpp differential voltage swing in driving 50-Ω output loads, 40-dB input dynamic range, 40-dB voltage gain, and 8-mV input sensitivity. The total power consumption is only 85 mW in 1.8-V supply and the chip feature die size is 700 µm× 400 µm.
    Relation Link: http://www.ieee.org/
    URI: http://nthur.lib.nthu.edu.tw/dspace/handle/987654321/71872
    Appears in Collections:[電機工程學系] 期刊論文

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