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    National Tsing Hua University Institutional Repository > 電機資訊學院 > 資訊工程學系 > 會議論文  >  Temperature-Constrained Fixed-Outline Floorplanning for 3D Ics


    Please use this identifier to cite or link to this item: http://nthur.lib.nthu.edu.tw/dspace/handle/987654321/79116


    Title: Temperature-Constrained Fixed-Outline Floorplanning for 3D Ics
    Authors: Ciao-Yu Hong;Wai-Kei Mak;Ting-Chi Wang
    教師: 王廷基
    麥偉基
    Date: 2012
    Publisher: The 17th Workshop on Synthesis And System Integration of Mixed Information technologies(SASIMI 2012)
    Relation: Proceedings of The Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI), Beppu, Oita, Japan, March 2012, pp. 457-459
    Keywords: Fixed-Outline
    Temperature
    Floorplanning
    3D-IC
    Abstract: Three-dimensional (3D) ICs are produced by stacking multiple dies and delivering inter-die signals with Through-Silicon Vias (TSVs). Typically, TSVs which deliver signals among dies are called signal TSVs, while those enhancing heat dissipation are called thermal TSVs. In this paper we present a temperature-constrained fixed-outline 3D-IC floorplanner which also simultaneously places signal and thermal TSVs to benefit wirelength and temperature reduction. Encouraging experimental results are shown to demonstrate the effectiveness and efficiency of our floorplanner.
    URI: http://sasimi.jp/new/sasimi2012/files/program/archive/program/R4_abst.html#R4-4
    http://sasimi.jp/new/sasimi2012/
    http://nthur.lib.nthu.edu.tw/dspace/handle/987654321/79116
    Appears in Collections:[積體電路設計技術研發中心] 會議論文
    [資訊工程學系] 會議論文

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