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    National Tsing Hua University Institutional Repository > 歷任校長 > 陳文村 (2006-2010)  > 會議論文 >  Design of A Parallel Theorem Prover for First Order Logic

    Please use this identifier to cite or link to this item: http://nthur.lib.nthu.edu.tw/dspace/handle/987654321/81599

    Title: Design of A Parallel Theorem Prover for First Order Logic
    Authors: Chen, W.-T.;Chou, T.-R.;Kuen-Rong Hsieh;Liu, H.-J.
    教師: 陳文村
    Date: 1991
    Publisher: Institute of Electrical and Electronics Engineers
    Relation: COMPSAC 91 - THE FIFTEENTH ANNUAL INTERNATIONAL COMPUTER SOFTWARE & APPLICATIONS CONFERENCE, PROCEEDINGS, Institute of Electrical and Electronics Engineers, Tokyo, Japan, 11-13 Sep. 1991, Pages 275-280
    Keywords: formal logic
    logic programming
    parallel algorithms
    theorem proving
    Abstract: The design of a parallel theorem prover for first-order logic is described. The parallel theorem algorithm is based on the divide-and-conquer strategy. The concept of restricted substitution is used to reduce the number of ground clauses generated during the operation of this theorem prover. In this manner, the ground clause set generated by the theorem prover will be much smaller than that generated directly by Herbrand universe.
    Relation Link: http://www.ieee.org/index.html
    URI: http://nthur.lib.nthu.edu.tw/dspace/handle/987654321/81599
    Appears in Collections:[陳文村 (2006-2010) ] 會議論文
    [資訊工程學系] 會議論文

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