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    National Tsing Hua University Institutional Repository > 電機資訊學院 > 電機工程學系 > 期刊論文 >  A Novel Low Gate-Count Pipeline Topology with Multiplexer-Flip- Flops for Serial Link

    Please use this identifier to cite or link to this item: http://nthur.lib.nthu.edu.tw/dspace/handle/987654321/83470

    Title: A Novel Low Gate-Count Pipeline Topology with Multiplexer-Flip- Flops for Serial Link
    Authors: Wei-Yu Tsai;Ching-Te Chiu;Jen-Ming Wu;Shawn S.H. Hsu;Yar-Sun Hsu
    教師: 吳仁銘
    Date: 2012
    Publisher: Institute of Electrical and Electronics Engineers
    Relation: IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, Institute of Electrical and Electronics Engineers, Volume 59, Issue 11, NOV 2012, Pages 2600-2610
    0.18-MU-M CMOS
    Abstract: This paper proposes multiplexer-flip-flops (MUX-FFs) to be a high-throughput and low-cost solution for serial link transmitters. We also propose multiplexer-latches (MUX-Latches) that possess the logic function of combinational circuits and storing capacity of sequential circuits. Adopting the pipeline with MUX-FFs, which are composed of cascaded latches and MUX-Latches, many latch gates for sequencing can be removed. Analysis and simulation results show that an 8-to-1 serializer in the pipeline topology with MUX-FFs reduces 52% gate-count compared to that in the traditional pipeline topology. To verify the functions of the proposed design, two chips are implemented with the proposed 4-to-1 MUX-FF and 8-to-1 serializer with MUX-FFs in 90 nm CMOS technology. The measured results show that the MUX-FF and the proposed serializer with MUX-FFs are almost bit-error-free (with), operating at up to 6 Gbits/s and 12 Gbit/s, respectively.
    Relation Link: http://www.ieee.org/
    URI: http://nthur.lib.nthu.edu.tw/dspace/handle/987654321/83470
    Appears in Collections:[電機工程學系] 期刊論文
    [積體電路設計技術研發中心] 期刊論文
    [通訊工程研究所] 期刊論文

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