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    National Tsing Hua University Institutional Repository > 電機資訊學院 > 電機工程學系 > 期刊論文 >  A built-in self-diagnosis and repair design with fail pattern identification for memories


    Please use this identifier to cite or link to this item: http://nthur.lib.nthu.edu.tw/dspace/handle/987654321/83578


    Title: A built-in self-diagnosis and repair design with fail pattern identification for memories
    Authors: C.-L. Su;R.-F. Huang;C.-W. Wu;K.-L. Luo;W.-C. Wu
    教師: 吳誠文
    Date: 2010
    Publisher: Institute of Electrical and Electronics Engineers
    Relation: IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, Institute of Electrical and Electronics Engineers, Volume 19, Issue 12, DEC 2010, Pages 2184-2194
    Keywords: EMBEDDED-MEMORY
    YIELD
    ONLINE
    Abstract: With the advent of deep-submicrometer VLSI technology, the capacity and performance of semiconductor memory chips is increasing drastically. This advantage also makes it harder to maintain good yield. Diagnostics and redundancy repair methodologies thus are getting more and more important for memories, including embedded ones that are popular in system chips. In this paper, we propose an efficient memory diagnosis and repair scheme based on fail-pattern identification. The proposed diagnosis scheme can distinguish among row, column, and word faults, and subsequently apply the Huffman compression method for fault syndrome compression. This approach reduces the amount of data that need to be transmitted from the chip under test to the automatic test equipment (ATE) without losing fault information. It also simplifies the analysis that has to be performed on the ATE. The proposed redundancy repair scheme is assisted by fail-pattern identification approach and a flexible redundancy structure. The area overhead for our built-in self-repair (BISR) design is reasonable. Our repair scheme uses less redundancy than other redundancy schemes under the same repair rate requirement. Experimental results show that the area overhead of the BISR design is only 4.1% for an 8 K x 64 memory and is in inverse proportion to the memory size.
    Relation Link: http://www.ieee.org/
    URI: http://nthur.lib.nthu.edu.tw/dspace/handle/987654321/83578
    Appears in Collections:[電機工程學系] 期刊論文
    [電腦與通訊科技研發中心] 期刊論文
    [資訊工程學系] 期刊論文

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