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    Please use this identifier to cite or link to this item: http://nthur.lib.nthu.edu.tw/dspace/handle/987654321/83579

    Title: SOC test architecture and method for 3D Ics
    Authors: C.-Y. Lo;Y.-T. Hsing;L.-M. Denq;C.-W. Wu
    教師: 吳誠文
    Date: 2010
    Publisher: Institute of Electrical and Electronics Engineers
    Relation: IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, Institute of Electrical and Electronics Engineers, Volume 29, Issue 10, OCT 2010, Pages 1645-1649
    Keywords: INTEGRATION
    Abstract: 3-D integration provides another way to put more devices in a smaller footprint. However, it also introduces new challenges in testing. Flexible test architecture named test access control system for 3-D integrated circuits (TACS-3D) is proposed for 3-D integrated circuits (IC) testing. Integration of heterogeneous design-for-testability methods for logic, memory, and through-silicon via (TSV) testing further reduces the usage of test pins and TSVs. To highly reuse pre-bond test circuits in post-bond test, an innovative linking mechanism shares TSVs and test pins of the 3-D IC. No matter how many layers are there in the 3-D IC, a large portion of TSVs and test pins is reserved for data application. Therefore, smaller post-bond test time is expected. A test chip composed of a network security processor platform is taken as an example. Less than 0.4% test overhead increases in area and time between 2-D and 3-D cases. Compared with the instinctively direct access, TACS-3D reveals up to 54% test time improvement under the same TSV usage.
    Relation Link: http://www.ieee.org/
    URI: http://nthur.lib.nthu.edu.tw/dspace/handle/987654321/83579
    Appears in Collections:[電機工程學系] 期刊論文
    [電腦與通訊科技研發中心] 期刊論文
    [資訊工程學系] 期刊論文

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