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    National Tsing Hua University Institutional Repository > 電機資訊學院 > 電機工程學系 > 期刊論文 >  A memory built-in self-repair scheme based on configurable spares


    Please use this identifier to cite or link to this item: http://nthur.lib.nthu.edu.tw/dspace/handle/987654321/83581


    Title: A memory built-in self-repair scheme based on configurable spares
    Authors: M. Lee;L.-M. Denq;C.-W. Wu
    教師: 吳誠文
    Date: 2011
    Publisher: Institute of Electrical and Electronics Engineers
    Relation: IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, Institute of Electrical and Electronics Engineers, Volume 30, Issue 6, JUN 2011, Pages 919-929
    Keywords: REDUNDANCY ANALYSIS
    INFRASTRUCTURE IP
    2-D REDUNDANCY
    ALGORITHM
    YIELD
    SIMULATION
    ARRAYS
    RAMS
    Abstract: There is growing need for embedded memory builtin self-repair (MBISR) due to the introduction of more and more system-on-chip (SoC) and other highly integrated products, for which the chip yield is being dominated by the yield of on-chip memories, and repairing embedded memories by conventional off-chip schemes is expensive. Therefore, we propose an MBISR generator called BRAINS+, which automatically generates register transfer level MBISR circuits for SoC designers. The MBISR circuit is based on a redundancy analysis (RA) algorithm that enhances the essential spare pivoting algorithm, with a more flexible spare architecture, which can configure the same spare to a row, a column, or a rectangle to fit failure patterns more efficiently. The proposed MBISR circuit is small, and it supports at-speed test without timing-penalty during normal operation, e.g., with a typical 0.13 mu m complementary metal-oxide-semiconductor technology, it can run at 333 MHz for a 512 Kb memory with four spare elements (rows and/or columns), and the MBISR area overhead is only 0.36%. With its low area overhead and zero test-time penalty, the MBISR can easily be applied to multiple memories with a distributed RA scheme. Compared with recent studies, the proposed scheme is better in not only test-time but also area overhead.
    Relation Link: http://www.ieee.org/
    URI: http://nthur.lib.nthu.edu.tw/dspace/handle/987654321/83581
    Appears in Collections:[電機工程學系] 期刊論文
    [電腦與通訊科技研發中心] 期刊論文
    [資訊工程學系] 期刊論文

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