National Tsing Hua University Institutional Repository:Speeding up emulation based diagnosis techniques for logic cores
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    NTHUR > College of Electrical Engineering and Computer Science > Department of Electrical Engineering > EE Journal / Magazine Articles  >  Speeding up emulation based diagnosis techniques for logic cores


    Please use this identifier to cite or link to this item: http://nthur.lib.nthu.edu.tw/dspace/handle/987654321/83582


    Title: Speeding up emulation based diagnosis techniques for logic cores
    Authors: S.-K. Lu;S.-Y. Huang;C.-W. Wu;Y.-M. Chen
    Teacher: 吳誠文
    Date: 2011
    Publisher: Institute of Electrical and Electronics Engineers
    Relation: IEEE DESIGN & TEST OF COMPUTERS, Institute of Electrical and Electronics Engineers, Volume 28, Issue 4, Special Issue SI, JUL-AUG 2011, Pages 88-97
    Keywords: HARDNESS EVALUATION
    FAULT INJECTION
    CIRCUITS
    LOCATION
    Abstract: This article proposes a new approach for an FPGA-based emulation system for IC fault diagnosis that incorporates three speedup techniques: circuit partitioning, fault-injection elements (using a novel design), and a fault-injection scan chain. Experimental results in terms of hardware overhead and emulation time for ISCAS-85 benchmark circuits are compared with previous works to highlight the 33× speedup and 44% reduced overhead of this proposed system.
    Relation Link: http://www.ieee.org/
    URI: http://nthur.lib.nthu.edu.tw/dspace/handle/987654321/83582
    Appears in Collections:[Department of Electrical Engineering] EE Journal / Magazine Articles
    [Computer and Communication Research Center ] CCRC Journal / Magazine Articles
    [Department of Computer Science] CS Journal / Magazine Articles

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