National Tsing Hua University Institutional Repository:Yield enhancement by bad-die recycling and stacking with though-silicon vias
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    National Tsing Hua University Institutional Repository > 電機資訊學院 > 電機工程學系 > 期刊論文 >  Yield enhancement by bad-die recycling and stacking with though-silicon vias


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    题名: Yield enhancement by bad-die recycling and stacking with though-silicon vias
    作者: Y.-F. Chou;D.-M. Kwai;C.-W. Wu
    教師: 吳誠文
    日期: 2011
    出版者: Institute of Electrical and Electronics Engineers
    關聯: IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, Institute of Electrical and Electronics Engineers, Volume 19, Issue 8, AUG 2011, Pages 1346-1356
    关键词: Bad-die recycling
    design for repair
    3-D integrated circuit (IC)
    through silicon via (TSV)
    wafer-level packaging
    摘要: 3-D integration provides a means to overcome the difficulties in design and manufacturing of system-on-chip (SOC) and memory products. Introducing a short vertical interconnect, called through-silicon via (TSV), makes it feasible to repair and recycle bad dies by stacking. We propose a method to accomplish this using a dual-TSV hardwired switch (DTHS) in which the via-hole location is programmable. With the DTHS, we activate a spare and establish inter-die routing. The spare is nothing but a good part in another bad die. To be 3-D reparable, the design is partitioned into disjoint parts. The effort for the modification is minor in view of that a typical SOC is readily composed of modules with predefined functions and supply voltages. The DTHS is used: 1) to shut off power connections of both failed and unused parts; 2) to disconnect their signal paths; and 3) to redirect them to the selected good parts in the stacked dies. Despite the speed is degraded due to the extra load incurred by the DTHS, our simulation shows that the increase in delay time can be limited below 100 ps with an over-designed buffer which occupies 0.8% of the area of a 30 mu m TSV, using a 65-nm CMOS process. The performance degradation turns out to be a necessary evil, since the increased height of the die stack leads to a thermal conductivity poorer than its 2-D counterpart. The 3-D patch die helps to shorten time-to-market and turn the irreparable dies profitable.
    相関连結: http://www.ieee.org/
    URI: http://nthur.lib.nthu.edu.tw/dspace/handle/987654321/83583
    显示于类别:[電機工程學系] 期刊論文
    [電腦與通訊科技研發中心] 期刊論文
    [資訊工程學系] 期刊論文

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