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    National Tsing Hua University Institutional Repository > 電機資訊學院 > 電機工程學系 > 期刊論文 >  A High Density MTP Cell with Contact Coupling Gates by Pure CMOS Logic Process


    Please use this identifier to cite or link to this item: http://nthur.lib.nthu.edu.tw/dspace/handle/987654321/83622


    Title: A High Density MTP Cell with Contact Coupling Gates by Pure CMOS Logic Process
    Authors: Haw-Yun Wu;Cheng-Wei Tsai;Chiu-Wang Lien;Chih, Y.-D.;Chrong Jung Lin
    教師: 林崇榮
    Date: 2011
    Publisher: Institute of Electrical and Electronics Engineers
    Relation: IEEE ELECTRON DEVICE LETTERS, Institute of Electrical and Electronics Engineers, Volume 32, Issue 10, OCT 2011, Pages 1352-1354
    Keywords: FULLY COMPATIBLE PROCESS
    EEPROM
    Abstract: In this letter, we propose a new fully logic-process-compatible multitime programmable (MTP) memory cell for high-density logic nonvolatile memory (NVM) applications. A very small logic NVM MTP cell has been demonstrated on pure 0.18-mu m CMOS process and logic design rules without extra masking and process steps. The MTP cell can be efficiently programmed and erased with a novel tiny contact coupling structure. Very small cell size, fast programming speed, and superior reliability characteristic make the new contact coupling gate MTP cell be one of the most promising solutions in advanced logic NVM application.
    Relation Link: http://www.ieee.org/
    URI: http://nthur.lib.nthu.edu.tw/dspace/handle/987654321/83622
    Appears in Collections:[電機工程學系] 期刊論文
    [電子工程研究所] 期刊論文

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