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    NTHUR > College of Electrical Engineering and Computer Science > Department of Electrical Engineering > EE Journal / Magazine Articles  >  A High Density MTP Cell with Contact Coupling Gates by Pure CMOS Logic Process

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    Title: A High Density MTP Cell with Contact Coupling Gates by Pure CMOS Logic Process
    Authors: Haw-Yun Wu;Cheng-Wei Tsai;Chiu-Wang Lien;Chih, Y.-D.;Chrong Jung Lin
    Teacher: 林崇榮
    Date: 2011
    Publisher: Institute of Electrical and Electronics Engineers
    Relation: IEEE ELECTRON DEVICE LETTERS, Institute of Electrical and Electronics Engineers, Volume 32, Issue 10, OCT 2011, Pages 1352-1354
    Abstract: In this letter, we propose a new fully logic-process-compatible multitime programmable (MTP) memory cell for high-density logic nonvolatile memory (NVM) applications. A very small logic NVM MTP cell has been demonstrated on pure 0.18-mu m CMOS process and logic design rules without extra masking and process steps. The MTP cell can be efficiently programmed and erased with a novel tiny contact coupling structure. Very small cell size, fast programming speed, and superior reliability characteristic make the new contact coupling gate MTP cell be one of the most promising solutions in advanced logic NVM application.
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    Appears in Collections:[Department of Electrical Engineering] EE Journal / Magazine Articles
    [Institute of Electronics Engineering ] ENE Journal / Magazine Articles

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