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    National Tsing Hua University Institutional Repository > 電機資訊學院 > 電機工程學系 > 會議論文  >  A Novel Low Gate-Count Serializer Topology with Multiplexer- Flip-Flops


    Please use this identifier to cite or link to this item: http://nthur.lib.nthu.edu.tw/dspace/handle/987654321/83682


    Title: A Novel Low Gate-Count Serializer Topology with Multiplexer- Flip-Flops
    Authors: Wei-Yu Tsai;Ching-Te Chiu;Jen-Ming Wu;Shawn S.H. Hsu;Yar-Sun Hsu
    教師: 吳仁銘
    Date: 2012
    Publisher: Institute of Electrical and Electronics Engineers
    Relation: Circuits and Systems (ISCAS), 2012 IEEE International Symposium on, Seoul, 20-23 May 2012, Pages 245 - 248
    Keywords: Serializer
    Topology
    Multiplexer- Flip-Flops
    Abstract: This paper proposes Multiplexer-Flip-Flops (MUX-FFs) to be a high-throughput and low-cost solution for serial link transmitters. We also propose Multiplexer-Latches (MUX-Latches) that possess the logic function of combinational circuits and storing capacity of sequential circuits. Adopting the pipeline with MUX-FFs, which are composed of cascaded latches and MUX-Latches, many latch gates for sequencing can be removed. Analysis shows that an 8-to-1 serializer in the pipeline topology with MUX-FFs reduces 52% gate-count compared to the traditional pipeline topology. To verify the function of the proposed design, a chips is implemented with the proposed 8-to-1 serializer with MUX-FFs in 90 nm CMOS technology. The measured results show that the proposed serializer with MUX-FFs are bit-error-free (with BER <; 10-12), operating at up to 12 Gbit/s.
    Relation Link: http://www.ieee.org/
    URI: http://nthur.lib.nthu.edu.tw/dspace/handle/987654321/83682
    Appears in Collections:[電機工程學系] 會議論文
    [積體電路設計技術研發中心] 會議論文
    [通訊工程研究所] 會議論文

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