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    Please use this identifier to cite or link to this item: http://nthur.lib.nthu.edu.tw/dspace/handle/987654321/83907

    Title: Is 3D integration an opportunity or just a hype?
    Authors: J.-F. Li;C.-W. Wu
    教師: 吳誠文
    Date: 2010
    Publisher: Institute of Electrical and Electronics Engineers
    Relation: 15th Asia and South Pacific Design Automation Conference, Taipei, TAIWAN, JAN 18-21, 2010
    Keywords: SILICON
    Abstract: Three-dimensional (3D) integration using through silicon via (TSV) is an emerging technology for integrated circuit designs. 3D integration technology provides numerous opportunities to designers looking for more cost-effective system chip solutions. In addition to stacking homogeneous memory dies, 3D integration technology supports heterogeneous integration of memories, logic, sensors, etc. It eases the interconnect performance limitation, provides higher functionality, results in small form factor, etc. On the other hand, there are challenges that should be overcome before volume production of TSV-based 3D ICs becomes possible, e.g., technological challenges, yield and test challenges, thermal and power challenges, infrastructure challenges, etc.
    Relation Link: http://www.ieee.org/
    URI: http://nthur.lib.nthu.edu.tw/dspace/handle/987654321/83907
    Appears in Collections:[電機工程學系] 會議論文
    [電腦與通訊科技研發中心] 會議論文
    [資訊工程學系] 會議論文

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