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    National Tsing Hua University Institutional Repository > 電機資訊學院 > 電機工程學系 > 會議論文  >  AF-Test: Adaptive-frequency scan test methodology for small-delay defects

    Please use this identifier to cite or link to this item: http://nthur.lib.nthu.edu.tw/dspace/handle/987654321/83909

    Title: AF-Test: Adaptive-frequency scan test methodology for small-delay defects
    Authors: T.-Y. Lee;S.-Y. Huang;H.-J. Hsu;C.-W. Tzeng;C.-T. Huang;J.-J. Liu;H.-P. Ma;P.-C. Huang;J.-C. Bor;C.-W. Wu;C.-C. Tien;M. Wang
    教師: 吳誠文
    Date: 2010
    Publisher: Institute of Electrical and Electronics Engineers
    Relation: Proc. IEEE 25th Int. Symp. Defect and Fault Tolerance in VLSI Systems (DFT), Kyoto, 6-8 Oct. 2010, Pages 340-348
    Keywords: small-delay defects
    Abstract: Small delay defects, when escaping from traditional delay testing, could cause a device to malfunction in the field. To address this issue, we propose an adaptive-frequency test method, abbreviated as AF-test. In this method, versatile test clocks can be generated on the chip by embedding an All-Digital Phase-Locked Loop (ADPLL) into the circuit under test (CUT). Instead of measuring the exact propagation delay associated with each test pattern like previous time-consuming failing frequency signature based analysis, we test only up to three different test clock frequencies for each test pattern to provide the benefit of fast characterization, and thereby making it suitable for volume production test. We have successfully demonstrated the AF-test on an in-house wireless test platform called HOY system using fabricated chips. This method can not only detect small delay defects effectively but also provide a grading scheme for those marginal chips that might have the reliability problem.
    Relation Link: http://www.ieee.org/
    URI: http://nthur.lib.nthu.edu.tw/dspace/handle/987654321/83909
    Appears in Collections:[電機工程學系] 會議論文
    [電腦與通訊科技研發中心] 會議論文
    [資訊工程學系] 會議論文

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