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    National Tsing Hua University Institutional Repository > 電機資訊學院 > 電機工程學系 > 會議論文  >  A test integration methodology for 3D integrated circuits

    Please use this identifier to cite or link to this item: http://nthur.lib.nthu.edu.tw/dspace/handle/987654321/83911

    Title: A test integration methodology for 3D integrated circuits
    Authors: C.-W. Chou;J.-F. Li;J.-J. Chen;D.-M. Kwai;Y.-F. Chou;C.-W. Wu
    教師: 吳誠文
    Date: 2010
    Publisher: Institute of Electrical and Electronics Engineers
    Relation: Proc. 19th IEEE Asian Test Symp. (ATS), Shanghai, 1-4 Dec. 2010, Pages 377-382
    Keywords: 3D
    Abstract: The three-dimensional (3D) integration technology using through silicon via (TSV) provides many benefits over the 2D integration technology. Although many different manufacturing technologies for 3D integrated circuits (ICs) have been presented, some challenges should be overcome before the volume production of 3D ICs. One of the challenges is the testing of 3D ICs. This paper proposes test integration interfaces for controlling the design-for-test circuits in the dies of a 3D IC. The test integration interfaces can support the pre-bond, known-good stack, and post-bond tests. The minimum number of required test pads of the proposed test interface for pre-bond test using is only four. Furthermore, the test interface is compatible with the IEEE 1149.1 standard for the board-level testing. Simulation results show that the area overhead of the proposed test interfaces for a 3D IC with two dies in which each die implements the function of ITC'99 b19 benchmark is only about 0.15%.
    Relation Link: http://www.ieee.org/
    URI: http://nthur.lib.nthu.edu.tw/dspace/handle/987654321/83911
    Appears in Collections:[電機工程學系] 會議論文
    [電腦與通訊科技研發中心] 會議論文
    [資訊工程學系] 會議論文

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