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    National Tsing Hua University Institutional Repository > 電機資訊學院 > 電機工程學系 > 會議論文  >  A built-in self-test scheme for the post-bond test of TSVs in 3D Ics


    Please use this identifier to cite or link to this item: http://nthur.lib.nthu.edu.tw/dspace/handle/987654321/83914


    Title: A built-in self-test scheme for the post-bond test of TSVs in 3D Ics
    Authors: Y.-J. Huang;J.-F. Li;J.-J. Chen;D.-M. Kwai;Y.-F. Chou;C.-W. Wu
    教師: 吳誠文
    Date: 2011
    Publisher: Institute of Electrical and Electronics Engineers
    Relation: 29th IEEE VLSI Test Symposium (VTS)/Workshop on Design for Reliability and Variability (DRV), Dana Point, CA, MAY 01-05, 2011
    Keywords: OPTIMIZATION
    3-DIMENSIONAL INTEGRATED-CIRCUITS
    DESIGN
    SOCS
    Abstract: Three-dimensional (3D) integration using through silicon via (TSV) has been widely acknowledged as one future integrated-circuit (IC) technology. A 3D IC including multiple dies connected with TSVs offers many benefits over current 2D ICs. However, the testing of 3D ICs is much more difficult than that of 2D ICs. In this paper, we propose a cost-effective built-in self-test circuit (BIST) to test TSVs of a 3D IC. The BIST scheme, arranging the TSVs into arrays similar to memory, has the features of low test/diagnosis time and low silicon area cost. Simulation results show that the area overhead of the BIST circuit implemented with 0.18 mu m CMOS technology for a 16x32 TSV array in which each TSV cell size is 45 mu m(2) is 2.24%. Also, the BIST needs only 130 clock cycles to test the TSV array with stuck-at faults. In comparison with the IEEE 1500-based test approach, the BIST scheme can achieve 85.2% area cost and 93.6% test time reduction.
    Relation Link: http://www.ieee.org/
    URI: http://nthur.lib.nthu.edu.tw/dspace/handle/987654321/83914
    Appears in Collections:[電機工程學系] 會議論文
    [電腦與通訊科技研發中心] 會議論文
    [資訊工程學系] 會議論文

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