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    National Tsing Hua University Institutional Repository > 電機資訊學院 > 電機工程學系 > 會議論文  >  A memory failure pattern analyzer for memory diagnosis and repair


    Please use this identifier to cite or link to this item: http://nthur.lib.nthu.edu.tw/dspace/handle/987654321/83920


    Title: A memory failure pattern analyzer for memory diagnosis and repair
    Authors: B.-Y. Lin;M. Lee;C.-W. Wu
    教師: 吳誠文
    Date: 2011
    Publisher: Institute of Electrical and Electronics Engineers
    Relation: 30th IEEE VLSI Test Symposium (VTS), HI, APR 23-25, 2012
    Keywords: memory diagnosis
    redundancy analysis
    built-in-self-repair (BISR)
    SOC
    yield improvement
    Abstract: As VLSI technology advances and memories occupy more and more area in a typical SOC, memory diagnosis has become an important issue. In this paper, we propose the Memory Failure Pattern Analyzer (MFPA), which is developed for different memories and technologies that are currently used in the industry. The MFPA can locate weak regions of the memory array, i.e., those with high failure rate. It can also be used to analyze faulty-cell/defect distributions automatically. We also propose a new defect distribution model which has 1-12 times higher accuracy than other theoretical models. Based on this model, we propose a defect-spectrum-based methodology to identify critical failure patterns from failure bitmaps. These failure patterns can further be translated to corresponding defects by our memory fault simulator (RAMSES) and physical-level failure analysis tool (FAME). In an industrial case, the MFPA fits the defect distribution with the proposed model, which has 12 times higher accuracy than the Poisson distribution. With our model, it further identifies two special failure patterns from 132,488 faulty 4-Mb macros in 1.2 minutes.
    Relation Link: http://www.ieee.org/
    URI: http://nthur.lib.nthu.edu.tw/dspace/handle/987654321/83920
    Appears in Collections:[電機工程學系] 會議論文
    [電腦與通訊科技研發中心] 會議論文
    [資訊工程學系] 會議論文

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