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    NTHUR > College of Electrical Engineering and Computer Science > Department of Electrical Engineering > EE Conference Papers >  Cost modeling and analysis for interposer-based three-dimensional IC

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    Title: Cost modeling and analysis for interposer-based three-dimensional IC
    Authors: Y.-W. Chou;P.-Y. Chen;M. Lee;C.-W. Wu
    Teacher: 吳誠文
    Date: 2011
    Publisher: Institute of Electrical and Electronics Engineers
    Relation: 30th IEEE VLSI Test Symposium (VTS), HI, APR 23-25, 2012
    Keywords: LEVEL
    Abstract: Three-dimensional (3D) integration has recently become a popular technology for integrated circuits (IC). 3D IC with the passive silicon interposer is currently the main trend in the industry, especially for processor-memory integration. Evaluating the economic efficiency of test operations in the interposer-based 3D IC thus is important. We propose a cost model for the Die-to-Wafer (D2W) and Die-to-Die (D2D) stacking, including manufacturing cost and test cost. A tool which is based on the proposed cost model is developed. We use this tool for cost analysis and for finding the most cost effective test flow. The results show that, in some applications, test flows including the iterative known-good stack (KGS) test and the pre-bond interposer test significantly reduce the cost, when the KGS test yield is lower than 98.2% and the pre-bond interposer test yield is lower than 99.38%. A Shmoo plot is depicted to show the lower bound of the yield of the final package level test, given the number of stacked dies and the final yield. For different applications, the proposed model evaluates the critical yield or cost values, which helps the designers to determine the most cost effective test flow and the system architecture.
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    Appears in Collections:[Department of Electrical Engineering] EE Conference Papers
    [Computer and Communication Research Center ] CCRC Conference Papers
    [Department of Computer Science] CS Conference Papers

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