English  |  正體中文  |  简体中文  |  Items with full text/Total items : 54371/62179 (87%)
Visitors : 9058359      Online Users : 82
RC Version 6.0 © Powered By DSPACE, MIT. Enhanced by NTHU Library IR team.
Scope Tips:
  • please add "double quotation mark" for query phrases to get precise results
  • please goto advance search for comprehansive author search
  • Adv. Search
    HomeLoginUploadHelpAboutAdminister Goto mobile version
    National Tsing Hua University Institutional Repository > 電機資訊學院 > 資訊工程學系 > 博碩士論文  >  考慮元件位移限制與密度的細部電路佈局與佈局合理化之演算法


    Please use this identifier to cite or link to this item: http://nthur.lib.nthu.edu.tw/dspace/handle/987654321/86637


    Title: 考慮元件位移限制與密度的細部電路佈局與佈局合理化之演算法
    Authors: 蔡至韋
    Tsai, Chih-Wei
    Description: GH02101062621
    碩士
    資訊工程學系
    Date: 2014
    Keywords: 電路佈局;密度
    detailed placement;density;displacement
    Abstract: 電路佈局在積體電路實體設計中是一個非常重要的步驟,現今的電路佈局程序通常包含到了全域佈局,合理化,細節佈局。全域佈局會產生一個已經最佳化某些目標的佈局結果,目標包含像是導線長度,可繞性,時序問題等等。合理化會移除所有的在佈局上元件的重疊且保證元件放在合法的位置上,細節佈局會根據全域佈局的結果在更進一步最佳化目標,像是導線長度。因為不只一個目標會在全域佈局中最佳化,所以在合理化和細部佈局中應該維護全域佈局結果的品質,在這篇論文中,我們提出了一個兩步驟的演算法架構來更進一步的最佳化導線長度並同時利用限制元件的最大移動距離來維護全域佈局結果的品質,在第一個步驟中,我們會有效的去消除由高單位密度所造成的懲罰因素。在第二個步驟中,我們會更進一步減少導線長度同時不去增加在上一個步驟中所消除的懲罰因素,在最後的實驗結果中,我們會展示出我們的細部佈局演算法在不同的最大移動距離限制和佈局目標使用率之下可以得到平均12.33%至15.12%的改進。
    Placement is one of the important steps in physical design. Modern placement process involves global placement, legalization, detailed placement.
    Global placement generate a placement solution with optimized objectives such as wire-length, routability, timing.
    Legalization removes cells overlap and makes sure the cells on the placement site.
    Detailed placement (DP) relocates cells to obtain a better placement solution.
    Since objectives are optimized in global placement, legalization and detailed placement should not only optimized its objective, but also preserved the global placement solution quality.
    In this thesis, we proposed a two-stage detailed placement algorithm for minimizing wire-length, also can preserve the global placement solution quality by constraining the cell displacement.
    In the first stage, we can effectively eliminate the penalty caused by high cell density.
    In the second stage, we further reduce wire-length without increasing the penalty.
    In experiments, we use ICCAD 2013 detailed placement contest [3] benchmarks, the result shows we could improve the global placement results 12.36% - 15.15% on average under different
    displacement constraint and target placement density.
    URI: http://nthur.lib.nthu.edu.tw/dspace/handle/987654321/86637
    Source: http://thesis.nthu.edu.tw/cgi-bin/gs/hugsweb.cgi?o=dnthucdr&i=sGH02101062621.id
    Appears in Collections:[資訊工程學系] 博碩士論文

    Files in This Item:

    File SizeFormat
    GH02101062621.pdf87KbAdobe PDF231View/Open


    在NTHUR中所有的資料項目都受到原著作權保護,僅提供學術研究及教育使用,敬請尊重著作權人之權益。若須利用於商業或營利,請先取得著作權人授權。
    若發現本網站收錄之內容有侵害著作權人權益之情事,請權利人通知本網站管理者(smluo@lib.nthu.edu.tw),管理者將立即採取移除該內容等補救措施。

    SFX Query

    與系統管理員聯絡

    DSpace Software Copyright © 2002-2004  MIT &  Hewlett-Packard  /   Enhanced by   NTU Library IR team Copyright ©   - Feedback