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    National Tsing Hua University Institutional Repository > 電機資訊學院 > 資訊工程學系 > 博碩士論文  >  針對工程變更命令電路利用布林可滿足性問題使邏輯差異最小化

    Please use this identifier to cite or link to this item: http://nthur.lib.nthu.edu.tw/dspace/handle/987654321/86647

    Title: 針對工程變更命令電路利用布林可滿足性問題使邏輯差異最小化
    Authors: 秦勢翔
    Chin, Shih-Hsiang
    Description: GH02101062626
    Date: 2014
    Keywords: 邏輯差異最小化
    ECO;logic difference
    Abstract: 在IC 設計工業中,隨著技術越來越進步,設計也越來越複雜,
    In the IC industry, chip design cycles are becoming more compressed, while designs
    themselves are growing in complexity. Functional specifications are often modified late
    in the design cycle, after placement and routing are complete. These trends necessitate
    efficient methods to handle late-stage engineering change orders (ECOs) to the functional
    specification, often in response to errors discovered after much of the implementation is
    finished. In this thesis, we propose a three-stage algorithm for generating a minimal logic
    difference between an original circuit and a modified circuit. Our method has three different
    stages and we perform them in order to produce a better patch. In the first phase, we search
    from the primary outputs to find structural equivalence between the original circuit and
    the modified circuit. In the second phase, we modify DeltaSyn[1] to use a SAT solver
    to identify logic equivalence near the input-side boundary of the changes. In the third
    phase, we create levels in each gate. According to levels, we check logically equivalent and
    choose replaced gates. After the three different stages, a gate-recycle[2] process performs
    the patch minimization in the final step. Encouraging experimental results are obtained by
    our method.
    URI: http://nthur.lib.nthu.edu.tw/dspace/handle/987654321/86647
    Source: http://thesis.nthu.edu.tw/cgi-bin/gs/hugsweb.cgi?o=dnthucdr&i=sGH02101062626.id
    Appears in Collections:[資訊工程學系] 博碩士論文

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